Semiconductor integrated circuit device and method for fabricating the same

ABSTRACT

Provided are a semiconductor integrated device and a method for fabricating the same. The semiconductor integrated circuit includes a semiconductor substrate including a first dopant, a first conductive layer pattern formed on the semiconductor substrate, an interlayer dielectric layer formed on the first conductive layer pattern, a second conductive layer pattern formed on the interlayer dielectric layer, and a first vacuum ultraviolet (VUV) blocking layer which blocks a VUV ray radiated to the semiconductor substrate.

This application is a continuation of U.S. application Ser. No.11/977,039, filed on Oct. 23, 2007, which is a divisional of U.S.application Ser. No. 11/429,370, filed on May 5, 2006 which claimspriority to Korean Patent Application No. 10-2005-0049016 filed on Jun.8, 2005, in the Korean Intellectual Property Office, the contents ofwhich are incorporated herein by reference in their entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor integrated circuitdevice and a method for fabricating the same, and more particularly,this application relates to a semiconductor integrated circuit devicehaving an improved operating characteristic and a method for fabricatingthe same.

2. Description of the Related Art

Semiconductor integrated circuit devices such as a system-on-chip (SOC),a microcontroller unit (MCU), and a display driver IC (DDI) include aplurality of peripheral devices such as a processor, a memory, a logiccircuit, an audio and image processing circuit, and various interfacecircuits. Thus, the semiconductor integrated circuit devices includetransistors having various driving voltages. For example, a high voltage(15-30V) driving transistor, an intermediate voltage (4-6V) drivingtransistor, and a low voltage (1-3V) driving transistor may be includedin a semiconductor integrated circuit device.

In particular, in order for a high voltage driving transistor to operatenormally even when a high voltage is applied, a breakdown voltagebetween a drain region of the high voltage driving transistor and asemiconductor substrate should be sufficiently high. Thus, a heavilydoped region of the drain region and a gate electrode are sufficientlyspaced apart to increase the breakdown voltage, and the dopingconcentration of a lightly doped region of the drain region and thesemiconductor substrate are reduced to enlarge a depletion region.Accordingly, the thickness of a gate insulating layer of the highvoltage driving transistor is larger than that of a gate insulatinglayer of the low voltage driving transistor.

After the high voltage driving transistor is manufactured, a back-endprocess of forming a multi-layered interconnection line and amulti-layered insulating layer is performed. A subsequent process isusually a plasma process such as conductive layer etching or photoresistlayer ashing. Vacuum ultraviolet (VUV) rays are generated during theplasma process to irradiate the semiconductor substrate, and thuspositive electric charges (or negative electric charges) are depositedon a gate insulating layer and/or a device isolation layer. Since thedoping concentration of the lightly doped region of the drain region andthe semiconductor substrate are low, a small change in electricalcharges caused by the VUV rays causes a significant change in thecharacteristic of the high voltage driving transistor.

For example, in the case of an NMOS high voltage driving transistor,positive electrical charges deposited on a gate insulating layer form achannel under the gate insulating layer, thereby increasing a drain-offcurrent (Idoff). In addition, positive electrical charges deposited on adevice isolation layer form an inversion layer on the device isolationlayer and a P-well interface and generate an isolation current (Isol)between a drain region and an N-well of an adjacent PMOS high voltagedriving transistor, thereby reducing an isolation effect.

SUMMARY OF THE INVENTION

The present invention provides a semiconductor integrated circuit devicehaving an improved operating characteristic.

The present invention also provides a method for fabricating asemiconductor integrated circuit device having an improved operatingcharacteristic.

The above stated objects as well as other objects, features andadvantages, of the present invention will become clear to those skilledin the art upon review of the following description.

According to an aspect of the present invention, there is provided asemiconductor integrated device comprising: a semiconductor substrateincluding a first dopant; a first conductive layer pattern formed on thesemiconductor substrate; an interlayer dielectric layer formed on thefirst conductive layer pattern; a second conductive layer pattern formedon the interlayer dielectric layer; and a first vacuum ultraviolet (VUV)blocking layer formed on the second conductive layer pattern and theinterlayer dielectric layer to block a VUV ray irradiated to thesemiconductor substrate.

In another embodiment, the semiconductor integrated circuit can furthercomprise a first oxide layer under the first VUV blocking layer.

In another embodiment, the first VUV blocking layer is formed of amaterial having a smaller band gap than silicon oxide.

In another embodiment, the first VUV blocking layer comprises nitride.

In another embodiment, the first VUV blocking layer is a SiN layer or aSiON layer.

In another embodiment, the first conductive layer pattern is a gateelectrode of a high voltage driving transistor.

In another embodiment, the high voltage driving transistor includessource/drain regions which are comprised of a lightly doped regionincluding a second dopant and a highly doped region, the lightly dopedregion being arranged at the gate electrode, formed in the semiconductorsubstrate and being of a different conductive type from thesemiconductor substrate and the highly doped region spaced apredetermined interval apart from the gate electrode, formed shallowerthan the lightly doped region, and being of a different conductivitytype from the semiconductor substrate.

In another embodiment, the dopant concentration of the first dopant isin a range of 1×10¹⁵-1×10¹⁷ atoms/cm³.

In another embodiment, the dopant concentration of the second dopant isin a range of 1×10¹⁴-1×10¹⁶ atoms/cm³.

In another embodiment, the semiconductor integrated circuit can furthercomprise an intermetallic dielectric layer formed on the first VUVblocking layer through plasma deposition.

In another embodiment, the intermetallic dielectric layer includes afirst dielectric layer and a second dielectric layer that aresequentially formed, the first dielectric layer having better gap-fillcharacteristic than the second dielectric layer.

In another embodiment, the semiconductor integrated circuit can furthercomprise a third conductive layer pattern formed on the intermetallicdielectric layer and a second VUV blocking layer formed on the entiresurface of the third conductive layer pattern and the intermetallicdielectric layer to block the VUV ray irradiated to the semiconductorsubstrate.

In another embodiment, the semiconductor integrated circuit can furthercomprise a second oxide layer under the second VUV blocking layer.

In another embodiment, the second VUV blocking layer is formed of amaterial having a smaller band gap than silicon oxide.

According to another aspect of the present invention, there is provideda method for fabricating a semiconductor integrated circuit, the methodcomprising forming a first conductive layer pattern on a semiconductorsubstrate including a first dopant, forming an interlayer dielectriclayer on the first conductive layer pattern, forming a second conductivelayer pattern on the interlayer dielectric; and forming a first vacuumultraviolet (VUV) blocking layer on the entire surface of the secondconductive layer pattern and the dielectric layer to block a WV rayirradiated to the semiconductor substrate.

In another embodiment, the method for fabricating a semiconductorintegrated circuit can further comprises forming a first oxide layerunder the first VUV blocking layer.

In another embodiment, the first VUV blocking layer is formed of amaterial having a smaller band gap than silicon oxide.

In another embodiment, the first VUV blocking layer comprises nitride.

In another embodiment, the first VUV blocking layer is a SiN layer or aSiON layer.

In another embodiment, the first conductive layer pattern is a gateelectrode of a high voltage driving transistor.

In another embodiment, the high voltage driving transistor includessource/drain regions which are comprised of a lightly doped regionincluding a second dopant and a highly doped region, the lightly dopedregion being arranged at the gate electrode, formed in the semiconductorsubstrate and being of a different conductivity type from thesemiconductor substrate and the highly doped region spaced apredetermined interval apart from the gate electrode, formed shallowerthan the lightly doped region, and being of a different conductivitytype from the semiconductor substrate.

In another embodiment, the dopant concentration of the first dopant isin a range of 1×10¹⁵-1×10¹⁷ atoms/cm³.

In another embodiment, the dopant concentration of the second dopant isin a range of 1×10¹⁴-1×10¹⁶ atoms/cm³.

In another embodiment, the method for fabricating a semiconductorintegrated circuit can further comprise forming an intermetallicdielectric layer on the first VUV blocking layer through plasmadeposition.

In another embodiment, the intermetallic dielectric layer includes afirst dielectric layer and a second dielectric layer that aresequentially twilled, the first dielectric layer having better gap-fillcharacteristic than the second dielectric layer.

In another embodiment, the method for fabricating a semiconductorintegrated circuit can further comprise twining a third conductive layerpattern on the intermetallic dielectric layer and a second VUV blockinglayer on the surface of the third conductive layer pattern and theintermetallic dielectric layer to block the VUV ray irradiated to thesemiconductor substrate.

In another embodiment, the method for fabricating a semiconductorintegrated circuit can further comprise forming a second oxide layerunder the second VUV blocking layer.

In another embodiment, the second VUV blocking layer is formed of amaterial having a smaller band gap than silicon oxide.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other features and advantages of the present inventionwill become more apparent by describing in detail preferred embodimentsthereof with reference to the attached drawings in which:

FIG. 1 is a layout of a semiconductor integrated circuit deviceaccording to a first embodiment of the present invention;

FIG. 2 is a cross-sectional view taken along line II-II′ in FIG. 1;

FIGS. 3A through 6B are views that illustrate the effect of thesemiconductor integrated circuit device according to the firstembodiment of the present invention;

FIG. 7 is a cross-sectional view of a semiconductor integrated circuitdevice according to a second embodiment of the present invention;

FIG. 8 is a cross-sectional view of a semiconductor integrated circuitdevice according to a third embodiment of the present invention;

FIGS. 9A through 9F are cross-sectional views that illustrate a methodfor fabricating a semiconductor integrated circuit device according tothe present invention; and

FIG. 10 shows a result of measuring drain-off currents after an NMOShigh voltage driving transistor and a PMOS transistor are manufacturedand a SiON layer is formed on a first interconnection line of each ofthe NMOS high voltage driving transistor and the PMOS transistor.

DETAILED DESCRIPTION OF THE INVENTION

Advantages and features of the present invention and methods ofaccomplishing the same may be understood more readily by reference tothe following detailed description of preferred embodiments and theaccompanying drawings.

Herein, a high voltage driving transistor is a transistor to which adriving voltage of 15-30V is applied and a low voltage drivingtransistor is a transistor to which a driving voltage of 3V or less isapplied. However, it is obvious that a specific value of the drivingvoltage can be readily changed by those skilled in the art.

FIG. 1 is a layout of a semiconductor integrated circuit deviceaccording to a first embodiment of the present invention. FIG. 2 is across-sectional view taken along line II-II′ in FIG. 1. Herein, asemiconductor integrated circuit device may be, but is not limited to,an inverter of a display driver IC (DDI).

Referring to FIGS. 1 and 2, a semiconductor integrated circuit device 1according to a first embodiment of the present invention includes asemiconductor substrate 100 having a first dopant, an NMOS high voltagedriving transistor 200, a PMOS high voltage driving transistor 300, andan upper-level layer structure 400.

The semiconductor substrate 100 may be a silicon substrate, a SOI(Silicon on Insulator) substrate, a gallium arsenic substrate, a silicongermanium substrate, a ceramic substrate, a quartz substrate, or a glasssubstrate for a display device. The semiconductor substrate 100 isusually a P-type substrate and a P-type epitaxial layer may be grown onthe semiconductor substrate 100.

A device isolation layer 110 formed on the semiconductor substrate 100defines an active region. An isolation layer may be a shallow trenchisolation (STI) or a field oxide isolation (FOX) formed by a localoxidation (LOCOS) process.

A P-well 120 and an N-well 130 may be formed to obtain a high voltagedriving transistor in the semiconductor substrate 100. In particular,the dopant concentration of a well used in a high voltage drivingtransistor is lower than that of a well used in a low voltage drivingtransistor. For example, the concentration of the first dopant of theP-well 120 and/or the N-well 130 may be in a range of 1×10¹⁵-1×10¹⁷atom/cm³.

The NMOS high voltage transistor 200 includes a gate electrode 220, agate insulating layer 210, a source region 230, and a drain region 240.

The gate electrode 220 is a conductive layer pattern extended in aspecific direction on the semiconductor substrate 100 and is insulatedfrom the semiconductor substrate 100 through the gate insulating layer210. The gate insulating layer 210 is usually made of silicon oxide(SiO_(x)). In particular, the thickness of a gate insulating layer of ahigh voltage driving transistor is larger than that of a gate insulatinglayer of a low voltage driving transistor. For example, the gateinsulating layer 210 of the NMOS high voltage transistor 200 may have athickness of 200-400 Å and a gate insulating layer of a low voltagetransistor may have a thickness of 30-150 Å. That is, the gate insultinglayer of the low voltage driving transistor is thin, thereby increasingthe driving speed of a semiconductor device, and the gate insulatinglayer 210 of the NMOS high voltage transistor 200 is thick, therebyhaving a sufficiently high proof stress level at a high voltage of 15Vor higher.

The source region 230 and the drain region 240 are arranged at bothsidewalls of the gate electrode 220. In particular, the source region230 and the drain region 240 of the NMOS high voltage driving transistor200 forms a mask islanded double diffused drain (MIDDD) structure forhigh voltage driving. That is, lightly doped regions 232 and 242 havinga second dopant are arranged in the gate electrode 220, and thus areformed in the semiconductor substrate 100, and heavily doped regions 234and 244 are spaced apart from the gate electrode 220 by a predeterminedinterval and are formed shallower than the lightly doped regions 232 and242. A breakdown voltage can be increased when the heavily doped regions234 and 244 to which a high voltage is applied are spaced apart from thegate electrode 220 by a sufficiently large interval.

In particular, the dopant concentration of the lightly doped regions 232and 242 of the NMOS high voltage driving transistor 200 are lower thanthose of lightly doped regions used in a low voltage driving transistor.For example, the concentration of the first dopant in the lightly dopedregions 232 and 242 may be in a range of 1×10¹⁴-1×10¹⁶ atom/cm³. Assuch, if the P-well 120 and the lightly doped regions 232 and 242 arelightly doped, the width of a depletion region at boundaries between theP-well 120 and the lightly doped regions 232 and 242 increases. Since abreakdown voltage sufficiently increases, a stable operation is possibleeven when a high voltage is applied to the drain region 240.

Although the source region 230 and the drain region 240 form an MIDDDstructure in the first embodiment of the present invention, they mayhave a lightly diffused drain (LDD) structure, a mask LDD (MLDD)structure, or a lateral double-diffused MOS (LDMOS) structure as long asthey are suitable for high voltage driving.

The PMOS high voltage driving transistor 300 includes a gate electrode320, a gate insulating layer 310, a source region 330, and a drainregion 340. The PMOS high voltage driving transistor 300 iscomplementary to the NMOS high voltage driving transistor 200 and anexplanation thereof will not be given.

The upper-level layer structure 400 includes an interlayer dielectriclayer 410, a contact 423, a first interconnection line 430, a firstvacuum ultraviolet (VUV) blocking layer 440, a first intermetallicdielectric layer 450, a first via 463, a second interconnection line470, a second intermetallic dielectric layer 480, a second via 493, athird interconnection line 495, and a passivation layer 496.

The interlayer dielectric layer 410 is formed on the NMOS high voltagedriving transistor 200, the PMOS high voltage driving transistor 300,and the semiconductor substrate 100. The interlayer dielectric layer 410is formed of a low dielectric constant dielectric material. By using alow dielectric constant dielectric material for the interlayerdielectric layer 410, may be at least one selected from the groupconsisting of, for example, a flowable oxide (FOX) layer, a torenesilazene (TOSZ) layer, a undoped silicate glass (USG) layer, aborosilicate glass (BSG) layer, a phosphosilicate glass (PSG) layer, aborophosphosilicate glass (BPSG) layer, a plasma enhancedtetraethylorthosilicate (PE-TEOS) layer, a fluoride silicate (FSG)layer, a high density plasma (HDP) layer, a plasma enhanced oxide, and astack layer of these layers. The overall dielectric constant of aninterconnection line of the semiconductor integrated circuit device 1and a resistance-capacitance (RC) delay can be reduced.

In the first embodiment of the present invention, the interlayerdielectric layer 410 includes a PEOX layer 411, a BPSG layer 412, and aPETEOS layer 413. Here, the PEOX layer 411 is used as a buffer layer andthe BPSG layer 412 has a superior gap-fill characteristic and thusreduces a step caused by the gate electrodes 220 and 320. The PETEOSlayer 413 provides superior throughput and thus, the interlayerdielectric layer 410 can be formed fast to a predetermined thickness.

The contact 423 is formed in a predetermined region of the interlayerdielectric layer 410 to electrically connect the source/drain regions230, 240, 330, 340, the gate electrodes 220 and 320 of the NMOS and PMOShigh voltage driving transistors 200 and 300 and the firstinterconnection line 430. The contact 423 may be formed of a metalmaterial such as copper, titanium, or tungsten.

In addition, a first barrier pattern 422 may be formed around thecontact 423 to prevent a material of the contact 423 from being diffusedto the interlayer dielectric layer 410. The first barrier pattern 422may be formed of Ti, TiN, Ti/TiN, Ta, TaN, Ta/TaN, or Ta/TiN.

The first interconnection line 430 is formed on the interlayerdielectric layer 410 and is a conductive layer pattern connected to thesource/drain regions 230, 240, 330, 340, the gate electrodes 220 and 320of the NMOS and PMOS high voltage driving transistors 200 and 300. Thefirst interconnection line 430 may be formed of aluminum to a thicknessof about 5000 Å. Although not shown, when the first interconnection line430 is an aluminum interconnection line, an adhesion film may be furtherformed of Ti/TiN between the first interconnection line 430 and thecontact 423 to improve the adhesion between the first interconnectionline 430 and the contact 423, and an anti-reflection coating film may befurther formed of Ti, TiN, or Ti/TiN on the first interconnection line430 to prevent a diffuse reflection of aluminum during aphotolithography process.

In the first embodiment of the present invention, the firstinterconnection line 430 serves for applying a ground voltage to thesource region 230 of the NMOS high voltage driving transistor 200, apower supply voltage to the source region 330 of the PMOS high voltagedriving transistor 300, and a predetermined signal voltage to the drainregion 240 of the NMOS high voltage driving transistor 200 and the drainregion 340 of the PMOS high voltage driving transistor 300.

The first VUV blocking layer 440 is formed on the entire surface of thefirst interconnection line 430 and the interlayer dielectric layer 410and blocks VUV rays irradiated to the semiconductor substrate 100. Thefirst VUV blocking layer 440 is formed of a material having a smallerband gap than silicon oxide (SiO_(x)). The gate insulating layers 210and 310 and/or the device isolation layer 110 are formed mainly ofsilicon oxide (SiO_(x)). Thus, when a VUV ray having greater energy thanthe band gap of silicon oxide (SiO_(x)) is irradiated, an electron-holepair (EHP) is formed and positive electric charges and/or negativeelectric charges are accumulated on the gate insulating layers 210 and310 and/or the device isolation layer 110. The deposited positiveelectric charges and/or negative electric charges increase a drain-offcurrent (Idoff) and an isolation current (Isol). Since the first VUVblocking layer 440 formed above the gate insulating layers 210 and 310and the device isolation layer 110 are formed of a material having asmaller band gap than silicon oxide (SiO_(x)), the VUV ray can beabsorbed before arriving at the gate insulating layers 210 and 310 andthe device isolation layer 110.

A material having a smaller band gap than silicon oxide (SiO_(x)) maybe, but is not limited to, a nitride layer or, in particular, a SiNlayer or SiON layer. The SiN layer may be formed to a thickness of 50 Åor more because of having a better VUV absorption characteristic thanthe SiON layer, and the SiON layer may be formed to a thickness of 500 Åor more. In addition, VUV absorption is improved as the thickness of theSiN layer or the SiON layer increases, but the thickness of the SiNlayer or the SiON layer may be adjusted according to the characteristicof the semiconductor integrated circuit device 1.

In addition, when the first VUV blocking layer 440 is a nitride layer,it can block external ions or moisture from entering the semiconductorsubstrate 100. The first intermetallic dielectric layer 450 and thesecond intermetallic dielectric layer 480 formed on the first VUVblocking layer 440 may include external ions or moisture due to amanufacturing process. The external ions or moisture may be diffused anddeposited on the gate insulating layers 210 and 310 and/or the deviceisolation layer 110. The deposited external ions or moisture increasethe drain-off current (Idoff) and the isolation current (Isol). Sincethe first VUV blocking layer 440 can block the external ions or moisturebefore the external ions or moisture arrive at the gate insulatinglayers 210 and 310 and/or the device isolation layer 110, the drain-offcurrent (Idoff) and the isolation current (Isol) can be reduced.

The first intermetallic dielectric layer 450 is formed on the first VUVblocking layer 440. The first intermetallic dielectric layer 450 has alow dielectric constant dielectric material, and may be at least onematerial selected from the group consisting of, for example, a flowableoxide (FOX) layer, a torene silazene (TOSZ) layer, a undoped silicateglass (USG) layer, a borosilicate glass (BSG) layer, a phosphosilicateglass (PSG) layer, a borophosphosilicate glass (BPSG) layer, a plasmaenhanced tetraethylorthosilicate (PE-TEOS) layer, a fluoride silicate(FSG) layer, a high density plasma (HDP) layer, a plasma enhanced oxide,and a stack layer of these layers. The overall dielectric constant of aninterconnection line of the semiconductor integrated circuit device 1and a resistance-capacitance (RC) delay can be reduced.

In the first embodiment of the present invention, an HDP layer 451 and aPETEOS layer 452 are sequentially deposited. In one embodiment, the HDPlayer 451 and the PETEOS layer 452 are formed by plasma deposition.Plasma deposition is advantageous in that deposition can be performed atlow temperature. Although VUV rays may be irradiated when using plasma,the first VUV blocking layer 440 absorbs the radiated VUV rays, therebypreventing the semiconductor integrated circuit device 1 from beingdamaged by the irradiated VUV rays.

In addition, the first intermetallic dielectric layer 450 may includeexternal ions or moisture, but the first VUV blocking layer 440 absorbsthe external ions or moisture, thereby preventing the semiconductorintegrated circuit device 1 from being damaged by the external ions ormoisture.

The HDP layer 451 has a superior gap-fill characteristic and thusreduces a step generated by the first interconnection line 430. ThePETEOS layer 452 provides superior throughput and thus, the firstintermetallic dielectric layer 450 can be formed quickly to apredetermined thickness.

The first via 463 is formed in a predetermined region of the firstintermetallic dielectric layer 450 to electrically connect the firstinterconnection line 430 and the second interconnection line 470. Thefirst via 463 may be formed of a metal material such as copper,titanium, or tungsten. A second barrier pattern 462 is foil ied aroundthe first via 463 to prevent a material of the first via 463 from beingdiffused to the first intermetallic dielectric layer 450.

The second interconnection line 470 is formed on the first intermetallicdielectric layer 450 and is electrically connected to the firstinterconnection line 430. The second interconnection line 470 may beformed mainly of aluminum. The second intermetallic dielectric layer 480is formed of a low dielectric constant material on the secondinterconnection line 470. The second via 493 is formed in apredetermined region of the second intermetallic dielectric layer 480 toelectrically connect the second interconnection line 470 and the thirdinterconnection line 495. The passivation layer 496 is formed on thethird interconnection line 495 to protect the semiconductor integratedcircuit device 1.

FIGS. 3A through 4B are views that illustrate the effect of thesemiconductor integrated circuit device according to the firstembodiment of the present invention. Here, FIGS. 3A and 4A indicate acase where the semiconductor integrated circuit device 1 does notinclude the first VUV blocking layer 440 and FIGS. 3B and 4B indicate acase where the semiconductor integrated circuit device 1 includes thefirst VUV blocking layer 440.

Referring to FIGS. 3A and 3B, if a VUV ray is irradiated to thesemiconductor integrated circuit device 1, positive electric charges areaccumulated on the gate insulating layer 210 of the NMOS high voltagedriving transistor 200. Once positive electric charges are accumulatedon the gate insulating layer 210, negative electric charges areaccumulated on the surface of the P-well 120, thereby forming aninversion layer 122. In particular, the inversion layer 122 can beeasily formed because the P-well 120 of the NMOS high voltage drivingtransistor 200 has low dopant concentration. Thus, a drain-off currentIdoff can be generated without a voltage greater than a thresholdvoltage being applied to the gate electrode 220.

On the other hand, since the irradiated VUV ray is absorbed by the firstVUV blocking layer 440 in FIGS. 3B and 4B, positive electric charges arenot accumulated on the gate insulating layer 210 of the NMOS highvoltage driving transistor 200. As a result, the drain-off current Idoffis not generated.

Referring to FIGS. 4A and 4B, once the VUV ray is irradiated to thesemiconductor integrated device 1 of FIG. 4A, positive electric chargesare accumulated on the device isolation layer 110 of the NMOS highvoltage driving transistor and the PMOS high voltage driving transistor(see 200 and 300 of FIG. 2). More specifically, when the deviceisolation layer 110 is a silicon oxide (SiO_(x)) layer, if the VUV rayhas an energy greater than the band gap of the silicon oxide layer, anelectron hole pair is formed and positive electric charges areaccumulated on the device isolation layer 110 adjacent to the P-well 120and the N-well 130. When positive electric charges are accumulated onthe device isolation layer 110, negative electric charges areaccumulated on the surfaces of the P-well 120 and the N-well 130adjacent to the device isolation layer 110. Thus, the inversion layer122 is formed in the P-well 120 and an accumulation layer 132 in whichpositive electric charges are accumulated is formed in the N-well 130.Since the P-well 120 and the N-well 130 have low dopant concentration,the inversion layer 122 and the accumulation layer 132 can be easilyformed. Thus, an isolation current Isol may be formed through theinversion layer 122 between the drain region 230 of the NMOS highvoltage driving transistor 200 and an N-well of the PMOS high voltagedriving transistor 300. As a result, the isolation between the NMOS highvoltage driving transistor 200 and the PMOS high voltage drivingtransistor 300 is degraded.

On the other hand, since the irradiated VUV ray is absorbed by the firstVUV blocking layer 440 in FIG. 4B, positive electric charges are notaccumulated on the device isolation layer 110 that electrically isolatesthe NMOS high voltage driving transistor 200 and the PMOS high voltagedriving transistor 300. As a result, an isolation current Isol is notgenerated.

Although only the case where the VUV ray is irradiated and thus positiveelectric charges are accumulated on the gate insulating layer 210 andthe device isolation layer 110 is described in FIGS. 3 and 4, it isobvious to those skilled in the art that negative electric charges canalso be accumulated by a substrate bias voltage applied to asemiconductor substrate. Thus, it is also obvious that a drain-offcurrent Idoff and an isolation current Isol may be generated in thesimilar way when negative electric charges are accumulated.

FIGS. 5A and 6B are views that illustrate the effect of thesemiconductor integrated circuit device according to the firstembodiment of the present invention, in each of which FIGS. 5A and 6Ashows a semiconductor integrated circuit without a first VUV blockinglayer 440 and FIGS. 5B and 6B shows a semiconductor integrated circuitwith a VUV blocking layer 440.

Referring to FIGS. 5A and 5B, in the semiconductor integrated circuit 1of FIG. 5A, external ions or moisture from a plurality of intermetallicdielectric layers (450 and 480 of FIG. 2) are diffused and thus negativeelectric charges may be accumulated on the gate insulating layer 310 ofthe PMOS high voltage driving transistor 300. Once negative electriccharges are accumulated on the gate insulating layer 310, negativeelectric charges are also accumulated, thereby forming an inversionlayer 134. In particular, the inversion layer 134 can be easily formedbecause the N-well 130 of the PMOS high voltage driving transistor 300has low dopant concentration. Thus, a drain-off current Idoff can begenerated without a voltage greater than a threshold voltage beingapplied to the gate electrode 320.

On the other hand, since external ions or moisture are absorbed by thefirst VUV blocking layer 440 formed of nitride in FIG. 5B, negativeelectric charges are not accumulated on the gate insulating layer 310 ofthe PMOS high voltage driving transistor 300.

Referring to FIG. 6A, external ions or moisture from a plurality ofintermetallic dielectric layers (see 450 and 480 of FIG. 2) are diffusedand thus negative electric charges may be accumulated on the deviceisolation layer 110 that electrically isolates the NMOS high voltagedriving transistor and the PMOS high voltage driving transistor (see 200and 300 of FIG. 2). Once negative electric charges are accumulated onthe device isolation layer 110, positive electric charges areaccumulated on the surfaces of the P-well 120 and the N-well 130adjacent to the device isolation layer 110. Thus, the inversion layer134 is foiined in the N-well 130 and the accumulation layer 124 in whichpositive electric charges are accumulated is formed in the P-well 120.The inversion 134 and the accumulation layer 124 can be easily formedbecause the P-well 120 and the N-well 130 of the NMOS high voltagedriving transistor and the PMOS high voltage driving transistor have lowdopant concentration. Thus, an isolation current Isol may be formedthrough the inversion layer 134 between the drain region 340 of the PMOShigh voltage driving transistor 300 and the P-well 120 of the NMOS highvoltage driving transistor 200. As a result, the isolation between theNMOS high voltage driving transistor 200 and the PMOS high voltagedriving transistor 300 is degraded.

On the other hand, in FIG. 6B, since the external ions or moisture areabsorbed by the first VUV blocking layer 440 formed of nitride, negativeelectric charges are not accumulated on the device isolation layer 110that electrically isolates the NMOS high voltage driving transistor 200and the PMOS high voltage driving transistor 300. As a result, anisolation current Isol is not generated.

Although only the case where negative electric charges are accumulatedon the gate insulating layer 310 and the device isolation layer 110 isdescribed in FIGS. 5 and 6, it is obvious to those skilled in the artthat positive electric charges can also be accumulated by a substratebias voltage applied to a semiconductor substrate. Thus, it is alsoobvious that a drain-off current Idoff and an isolation current Isol canbe generated in the similar manner when positive electric charges areaccumulated.

FIG. 7 is a cross-sectional view of a semiconductor integrated circuitdevice according to a second embodiment of the present invention.Components each having the same function for describing the embodimentsshown in FIGS. 2 are respectively identified by the same referencenumerals, and their repetitive description will be omitted.

Referring to FIG. 7, a semiconductor integrated circuit 2 according to asecond embodiment of the present invention is different from thesemiconductor integrated circuit 1 according to the first embodiment ofthe present invention in that a second VUV blocking layer 475 thatblocks VUV rays irradiated to the semiconductor substrate 100 is furtherformed on the entire surface of a second interconnection line 470 and asecond intermetallic dielectric layer 480. The second VUV blocking layer475 blocks the VUV rays irradiated to the semiconductor substrate 100,external ions, and moisture. The first VUV blocking layer 440 is foimedof a material having a smaller band gap than silicon oxide (SiO_(x)).For example, the first VUV blocking layer 440 may be, but is not limitedto, a SiN layer or a SiON layer as.

Since the first VUV blocking layer 440 and the second VUV blocking layer475 are founed in the semiconductor integrated circuit device 2according to the second embodiment of the present invention, thesemiconductor integrated circuit device 2 can be superior to thesemiconductor integrated circuit device 1 according to a firstembodiment of the present invention in terms of blocking VUV rays andabsorbing external ions and moisture.

In one embodiment, a VUV blocking layer may be formed only on the entiresurface of the second interconnection line 470 and the secondintermetallic dielectric layer 480. However, damage may be caused due toVUV rays irradiated during a process of manufacturing the firstintermetallic dielectric layer 450 or due to external ions and moistureincluded in the first intermetallic dielectric layer 450.

FIG. 8 is a cross-sectional view of a semiconductor integrated circuitdevice according to a third embodiment of the present invention.

Referring to FIG. 8, a semiconductor integrated circuit 3 according to athird embodiment of the present invention is different from thesemiconductor integrated circuit 1 according to the first embodiment ofthe present invention in that a first oxide layer 435 is furtherincluded between the entire surface of the first interconnection line430 and the interlayer dielectric layer 410 and the first VUV blockinglayer 440. The first oxide layer 435 serves as a buffer between theentire surface of the first interconnection line 430 and the interlayerdielectric layer 410 and the first VUV blocking layer 440.

In one embodiment, a second oxide layer and a second VUV blocking layercan be sequentially formed on the entire surface of a firstintermetallic dielectric layer and a second interconnection line.

FIGS. 9A through 9F are cross-sectional views illustrating a method forfabricating a semiconductor integrated circuit device according to thepresent invention.

Referring to FIG. 9A, the semiconductor substrate 100 is provided. Thedevice isolation layer 110 is formed on the semiconductor substrate 100to define an active region. The NMOS high voltage driving transistor 200and the PMOS high voltage driving transistor 300 are formed on theactive region.

Next, the interlayer dielectric 410 is formed on the NMOS high voltagedriving transistor 200, the PMOS high voltage driving transistor 300,and the semiconductor substrate 100. The interlayer dielectric layer 410may be formed of a low-k material. In this embodiment of the presentinvention, the PEOX layer 411, the BPSG layer 412, and the PETEOS layer413 are sequentially formed.

Next, contact holes 421 that expose the source/drain regions 230 and 240of the NMOS high voltage driving transistor 200 and the source/drainregions 330 and 340 of the PMOS high voltage driving transistor 300 areformed by performing a typical etching process on the interlayerdielectric layer 410.

Referring to FIG. 9B, a first barrier layer is conformally formed alongthe profile of the sides and bottoms of the contact holes 421 and thetop of the interlayer dielectric layer 410. The first barrier layer maybe formed of Ti, TiN, Ti/TiN, Ta, TaN, Ta/TaN, or Ta/TiN using chemicalvapor deposition (CVD) or sputtering.

Next, a metal layer is formed on the first barrier layer 440 bydepositing a conductive material such as Cu, Ti, or W to sufficientlyfill the contact holes 421. Here, it is preferable that Ti or W bedeposited using CVD or sputtering because Cu is likely to be diffused tothe interlayer dielectric layer 410.

Next, the metal layer and the first barrier layer 440 are polished usingchemical mechanical polishing (CMP) until the surface of the interlayerdielectric layer 410 is exposed, thereby forming a contact 423 thatfills the contact holes 421. At this time, the first barrier layerremains at the sidewalls and bottom of the contact 423 as a firstbarrier layer pattern 422.

Referring to FIG. 9C, a first interconnection line conductive layer isdeposited on the interlayer dielectric layer 410 and is then patterned,thereby forming a first interconnection line 430. Here, aluminum is usedfor the first interconnection line conductive layer and is depositedusing CVD or sputtering.

Although not shown, when the first interconnection line 430 is analuminum interconnection line, an adhesion film may be further formed ofTi/TiN between the first interconnection line 430 and the contact 423 toimprove the adhesion between the first interconnection line 430 and thecontact 423, and an anti-reflection coating film may be further formedof Ti, TiN, or Ti/TiN on the first interconnection line 430 to prevent adiffuse reflection of aluminum during a photolithography process.

Referring to FIG. 9D, the first VUV blocking layer 440 that blocks VUVrays irradiated to the semiconductor substrate 100 is formed on theentire surface of the first interconnection line 430 and the interlayerdielectric layer 410. For example, the first VUV blocking layer 440 isformed of a material having a smaller band gap than silicon oxide(SiO_(x)) such as nitride. In particular, a SiN layer or a SiON layermay be formed through CVD.

Referring to FIG. 9E, the first intermetallic dielectric layer 450 isformed on the first VUV blocking layer 440. In the first embodiment ofthe present invention, an HDP layer 451 and a PETEOS layer 452 aresequentially deposited. Here, the HDP layer 451 and the PETEOS layer 452are formed by plasma deposition. Plasma deposition is advantageous inthat deposition can be performed at low temperature. Although VUV raysmay be irradiated when using plasma, the first VUV blocking layer 440absorbs the radiated VUV rays, thereby preventing the semiconductorintegrated circuit device 1 from being damaged by the irradiated VUVrays.

Referring to FIG. 9F, a photoresist pattern 465 is formed on the firstintermetallic dielectric layer 450, thereby forming first via holes 461that expose the first interconnection line 430. Thereafter, thephotoresist pattern 465 is removed through an ashing process usinghigh-temperature oxygen plasma. VUV rays may be irradiated when usingplasma, but the first VUV blocking layer 440 absorbs the VUV rays andthus prevents the semiconductor integrated circuit 1 from being damaged.

Referring back to FIG. 2, a second barrier layer is conformally formedalong the profile of the sides and bottom of the first via holes 461 andthe top of the interlayer dielectric layer 410. Next, a metal layer isformed by depositing a conductive material such as Cu, Ti, or W on thefirst barrier layer to sufficiently fill the first via holes 461. Next,the metal layer and the second barrier layer are polished using CMPuntil the surface of the first intermetallic dielectric layer 450 isexposed, thereby forming the first via 463 that fills the first viaholes 461.

The second interconnection line 470 is formed on the first intermetallicdielectric layer 450. The second intermetallic dielectric layer 480, thesecond via holes 491, third barrier layer patterns 492, and a second via493 are formed.

The third interconnection line 495 is formed on the second intermetallicdielectric layer 480 and the passivation layer 496 that protects thesemiconductor integrated device 1 is formed on the third interconnectionline 495.

While the method of fabricating a semiconductor integrated circuitdevice according to an embodiment of the present invention has beendescribed, methods of fabricating semiconductor integrated circuitdevices according to other embodiments of the present invention can bereadily envisioned technologically by those skilled in the art. Thus, anexplanation thereof will not be given.

The experimental example described below is for illustrative purposesand other examples and applications can be readily envisioned by aperson of ordinary skill in the art.

EXPERIMENTAL EXAMPLE

Referring to FIG. 10, after forty-two NMOS high voltage drivingtransistors and forty-two PMOS high voltage driving transistors, eachhaving a width of 25 μm and a length of 4 μm, are formed, a SiON layerhaving a thickness of 260 Å is formed on a first interconnection line ineach of eleven NMOS high voltage driving transistors, N1 through N11,and eleven PMOS high voltage driving transistors, P1 through P11, a SiONlayer having a thickness of 600 Å is formed on a first interconnectionline in each of twenty-five NMOS high voltage driving transistors, N12through N36, and twenty-five PMOS high voltage driving transistors, P12through P36, and a SiON layer is not formed in a first interconnectionline in each of six NMOS high voltage driving transistors, N37 throughN42, and six PMOS high voltage driving transistors, P37 through P42.

Next, a drain-off current Idoff of each of the forty-two NMOS highvoltage driving transistors and the forty-two PMOS high voltage drivingtransistors is measured and the results are shown in FIG. 10.

Referring to FIG. 10, the x axis indicates a number of transistors andthe y axis indicates a drain-off current Idoff. In the experimentalexample, negative electric charges are accumulated on a gate insulatinglayer. Thus, the drain-off current Idoff of the NMOS high voltagedriving transistors N1 through N42 is constant at about 0.5 pA/μm. Onthe other hand, in the PMOS high voltage driving transistors, P1 throughP42, the thickness of the SiON layer increases, the drain-off currentIdoff decreases. That is, the drain-off current Idoff is about 5 pA/μmin the PMOS high voltage driving transistors, P37 through P42 having noSiON layer, the drain-off current Idoff is about 50 pA/μm in the PMOShigh voltage driving transistors P1 through P11 having a SiON layer witha thickness of 260 Å, and the drain-off current Idoff in the PMOS highvoltage driving transistors P12 through P36 having a SiON layer of 600 Åis similar to the drain-off current Idoff in the NMOS high voltagedriving transistors N1 through N42.

As described above, a semiconductor intergrated circuit device andmethod for fabricating the same according to the present inventionprovides at least the following advantages.

First, a VUV blocking layer prevents VUV rays from being irradiated to asemiconductor substrate and external ions or moisture from penetratingthe semiconductor substrate.

Second, by reducing a leakage current such as a drain-off current Idoffand an isolation current Isol, the operating characteristic of asemiconductor integrated circuit can be improved.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims. Therefore,it is to be understood that the above-described embodiments have beenprovided only in a descriptive sense and will not be construed asplacing any limitation on the scope of the invention.

1. A semiconductor integrated circuit comprising: a semiconductorsubstrate including a first dopant; a first conductive layer patternformed on the semiconductor substrate, the first conductive layerpattern being a gate electrode of a high voltage driving transistor; aninterlayer dielectric layer formed on the first conductive layerpattern; a second conductive layer pattern formed on the interlayerdielectric layer; and a first blocking layer having an insulatingproperty formed conformally on the second conductive layer pattern andthe interlayer dielectric layer to block a ray irradiated to thesemiconductor substrate.